This invention relates to signal generation, and in particular to a novel means and structure for generating a signal having a frequency of 2.sup.C Hz from a reference signal having a frequency of 2.sup.A .multidot.5.sup.B Hz.
It is often desired to generate or "synthesize" signals having desired frequencies. Various techniques for doing so are well known in the art. However, when it is desired to generate an output frequency which is highly stable and highly accurate, a relatively few signal generation techniques are available. To generate highly stable and accurate signals, a crystal, such as a quartz crystal, can be used in an oscillator circuit. The signal from the crystal oscillator circuit can either be used as is, or can be multiplied in order to obtain a reference signal having a frequency greater than the fundamental frequency of the crystal. Another technique is to use a phase lock loop in order to generate a highly stable and accurate frequency which is other than the frequency of the crystal element in the phase lock loop circuit. More complex techniques are also available, including direct frequency synthesis and the like, as is well known in the art. Such various frequency generation techniques are described, for example, by Noordanus, "Frequency Synthesizers--A Survey of Techniques", IEEE Transactions on Communication Technology, Vol. COM-17, No. 2, April 1969, pp. 257-271, which is hereby incorporated by reference.
In certain applications, such as direct digital frequency synthesis, it is highly advantageous to have a reference signal having a frequency which is an integral power of two. Such a signal could be generated using a crystal having an appropriate frequency, although there are several major disadvantages to this. One is that for a frequency of 2.sup.C Hz, with C=27 (134.217728 MHz), crystal oscillators are not highly stable, and thus drift in frequency over time. Secondly, their close-in phase noise is not as low as that provided by a lower frequency oscillator (such as 10 MHz). It would be highly advantageous, therefore, to provide such a signal having a frequency of 2.sup.C Hz which is derived from a signal having a more common frequency, such as 5 MHz, 10 MHz, etc., since circuits employing such reference oscillators are well known in the art and widely used, exhibit high stability, low close-in phase noise, and are easily calibrated. 10 MHz can be expressed as 2.sup.A .multidot.5.sup.B, where A=B=7.
One technique for performing this function in accordance with the prior art is to provide a phase lock loop circuit, as is shown in FIG. 1. Phase lock loop circuit 10 of FIG. 1 includes a 10 MHz reference signal source 11, as is well known in the art. Phase lock loop circuit 10 also includes voltage controlled oscillator (VCO) 14 which provides an output signal on output terminal 19 having a desired frequency. If this frequency is equal to 2.sup.27 Hz (134,217,728 Hz), it is seen that 128 Hz is the greatest common factor of the 10 MHz reference signal provided by reference signal source 11 and the 2.sup.27 Hz desired output signal to be generated by VCO 14, since 10 MHz equals 2.sup.7 .times.5.sup.7 Hz and 128=2.sup.7 Hz. Thus, in accordance with general phase lock loop techniques, it is necessary to provide a 128 Hz signal derived from the 10 MHz signal generator 11 to phase comparator 13, for comparison with a 128 Hz signal derived from VCO 14. In order to do this, the 10 MHz signal from signal generator 11 must be divided by a factor of 5.sup.7 by divider 12, and the output signal from VCO 14 must be divided by a factor of 2.sup.20 by divider 15. Means for dividing a signal by 2, (and thus powers of 2) and by 5, (and thus by powers of 5) are well known in the art. By applying two signals from dividers 12 and 15 to phase comparator 13, phase comparator 13 is able to generate an error signal which is applied to loop filter/amplifier 9, which in turn provides a signal to the control input lead of VCO 14 in order to control the output frequency of VCO 14. Thus, if the frequency of the output signal from VCO 14 is greater than the desired output frequency, phase detector 13 will provide an error signal so indicating, causing VCO 14 to lower its frequency. Conversely, should VCO 14 provide an output signal whose frequency is less than desired, phase detector 13 will provide an error signal to VCO 14, causing VCO 14 to increase its frequency. In this manner, a loop is established which phase locks the output frequency of VCO 14 at the desired frequency, in this case 2.sup.27 Hz.
However, this application of prior art phase lock loop principles requires the use of a very low frequency (128 Hz) signal for phase comparison, which would prevent simultaneously meeting desired spurious signal and phase noise requirements. This is because the desired loop bandwidth for phase noise concerns is approximately 100 Hz, which is far too wide to filter spurious products from a phase detector working at 128 Hz. Furthermore, other components, such as dividers and phase detectors, have residual phase noise which is additive to the signal passing through them, independent of frequency. Since a signal's phase noise level is a function of frequency (if one scales frequency by "N", phase noise scales by 20 log N), it is necessary to keep the frequency of all signals high enough that the phase noise of the signal is not degraded by additive noise of the components (divider, phase detector, etc.). Preferably, the residual noise of components is not greater than approximately 10 dB less than the phase noise of the signals being manipulated. Using standard available dividers and phase detectors, this frequency level is at least about 10 MHz. For example, if one used a phase detector at 128 Hz to control an oscillator at 2.sup.27 Hz (134.217728 MHz), then the residual phase noise of the phase detector would be scaled up by 120 dB at the oscillator. Given the phase noise performance of any known phase detector, this would drastically degrade phase noise at the oscillator.
As an alternative to the structure of FIG. 1, a fractional N loop could be used to lock oscillator 11 and VCO 14 together, in order to cause VCO 14 to provide the desired output frequency. Two types of fractional "N" loops exist; one compensates for phase comparison errors to reduce the level of spurious signals and one does not. The uncompensated method will yield spurious signals at 128 Hz offsets which can only be filtered by using loop bandwidths which provide unacceptable phase noise. Thus, spurious signal and phase noise requirements cannot be simultaneously met. Using a compensated fractional N loop would allow a bandwidth that is good for phase noise, but with inadequate suppression of spurious signals. Such fractional "N" loops are described, for example, in "The Common Denominators in Fractional N", Hassun, Microwaves and RF, June 1984, pp. 107-110; "Frequency Domain Yields its Data to Phase-Locked Synthesizer", Gibbs et al., Electronics, Apr. 27, 1977, pp. 107-113; "VLF Output, Low Phase Noise Make Synthesizer Attractive Test Tool", Communications Designer's Digest, August, 1969, pp. 46-49; and "Low-Noise Frequency Synthesizers Using Fractional N Phase-Locked Loops", Rohde, R. F. Design, January/February 1981, pp. 20-34.